Verification Plan (SVP) — ISO/IEC/IEEE 15289 — Plan | IEEE 29148 §6.6
Generated 2026-03-27 — UHT Journal / universalhex.org
| Ref | Requirement | Method | Tags |
|---|---|---|---|
| VER-METHODS-001 | Verify IFC-DEFS-001: Factory acceptance test measuring optical isolation breakdown voltage and signal transition time. Pass criteria: isolation exceeds 1500VDC, transition time less than 1ms. Test repeated after environmental qualification aging. Rationale: Optical isolation is the primary barrier between protection channels; failure to meet breakdown voltage could allow fault propagation between divisions, defeating redundancy. | Test | verification, rts, session-199 |
| VER-METHODS-002 | Verify IFC-DEFS-002: Integration test injecting trip signals from coincidence logic and measuring breaker opening time with oscilloscope on breaker auxiliary contacts. Pass criteria: breaker opens within 100ms. Verify train separation by confirming no voltage on opposite train circuits. Rationale: Trip breaker opening time is the final element in the 2.0s response time budget; direct measurement with oscilloscope provides traceable evidence of performance. | Test | verification, rts, session-199 |
| VER-METHODS-003 | Verify IFC-DEFS-003: Channel calibration test injecting known current signals at NIS output and verifying bistable processor receives correct value within 0.5 percent accuracy. Verify raceway separation by physical inspection per IEEE 384. Rationale: NIS-to-bistable signal integrity directly affects trip setpoint accuracy; any signal degradation at this interface shifts effective trip points. | Test | verification, rts, nis, session-199 |
| VER-METHODS-004 | Verify IFC-DEFS-004: End-to-end signal validation injecting calibrated current signals at process instrument transmitter output and verifying correct receipt at bistable processor input within specified accuracy band. Verify cable routing separation by walkdown inspection. Rationale: End-to-end calibration validates the cumulative accuracy of the process measurement chain from transmitter to bistable input. | Test | verification, rts, pis, session-199 |
| VER-METHODS-005 | Verify IFC-DEFS-005: Channel calibration test injecting known 4-20mA signals at each PIS transmitter output and measuring at ESF coincidence logic input. Pass: measured signal within ±0.25% of injected value after isolation. Verify minimum 24 inputs per channel by inspection of wiring drawings and point-to-point test. Rationale: Process instrumentation to ESFAS signal path accuracy affects ESF actuation setpoint reliability; verified at installation and each refueling outage. | Test | verification, esfas, session-201 |
| VER-METHODS-006 | Verify IFC-DEFS-006: End-to-end signal validation injecting calibrated neutron flux simulation signals at NIS detector preamplifier test inputs. Pass: ESF coincidence logic receives correct flux indication within ±1% of injected value, with no cross-channel signal coupling measured above -80dB. Rationale: NIS flux simulation verifies the complete signal path from detector preamplifier through conditioning to ESFAS input, covering range overlap transition zones. | Test | verification, esfas, session-201 |
| VER-METHODS-007 | Verify IFC-DEFS-007: Factory acceptance test measuring optical isolation breakdown voltage (pass: >=2500V per IEC 60747-5-5) and signal transition time (pass: <1ms measured at 10%-90% thresholds) for each ESF function output from coincidence logic to priority logic. Rationale: ESF coincidence-to-priority-logic isolation is critical for maintaining ESFAS availability; factory acceptance testing ensures qualification before installation. | Test | verification, esfas, session-201 |
| VER-METHODS-008 | Verify IFC-DEFS-008: Integration test measuring relay contact interrupting capacity under rated load (pass: >=10A at 125VDC without contact welding over 1000 cycles). Physical separation verified by inspection against IEEE 384 separation criteria with minimum 1-inch air gap or qualified barrier between Train A and Train B circuits. Rationale: Relay contacts must interrupt rated load current without welding over 100,000 cycles representing the design life of ESF actuations including surveillance tests. | Test | verification, esfas, session-201 |
| VER-METHODS-009 | Verify IFC-DEFS-009: Integration test actuating each subgroup relay and measuring time from relay energisation to confirmed equipment state change at Component Interface Module feedback input. Pass: feedback received within 500ms for all dry contact inputs. Functional grouping verified by inspection of subgroup assignment tables. Rationale: Subgroup relay-to-component actuation time must be verified to ensure ESF equipment achieves its safety function within the FSAR-assumed response time. | Test | verification, esfas, session-201 |
| VER-METHODS-010 | Verify IFC-DEFS-010: Timed sequence test injecting SI+LOOP signal and recording each load step timing. Pass: minimum 5-second interval between consecutive load connections, breaker close confirmation within 2 seconds of each step command, full sequence completion within 60 seconds. Rationale: Load sequencing timing prevents diesel generator overload during LOCA+LOOP; verification confirms each load step occurs within the designed interval. | Test | verification, esfas, session-201 |
| VER-METHODS-011 | Verify IFC-DEFS-011: Source range channel test injecting calibrated pulse signals through the triaxial cable at the detector well test connector. Pass: minimum 10:1 SNR at 0.1 cps equivalent, cable impedance measured at 50±5 ohms by TDR. Rationale: Source range pulse fidelity through triaxial cable directly affects pulse height discrimination and neutron/gamma separation accuracy during startup. | Test | verification, nis, session-201 |
| VER-METHODS-012 | Verify IFC-DEFS-012: Power range channel test injecting calibrated DC currents spanning 1E-11 to 1E-3 amps into upper and lower sections independently. Pass: signal conditioning output within ±1% of injected value, inter-section leakage below 1E-12 amps measured with opposite section grounded. Rationale: Power range upper/lower section independence is verified separately to confirm axial flux difference measurement capability for DNBR protection. | Test | verification, nis, session-201 |
| VER-METHODS-013 | Verify IFC-DEFS-013: HV power supply test measuring output voltage stability over 24 hours with rated detector load. Pass: ±0.1% stability, current limiting at 1mA±10%, shield continuity <1 ohm end-to-end. Rationale: HV supply stability directly affects detector gain; 24-hour test duration bounds the surveillance interval and captures thermal cycling effects. | Test | verification, nis, session-201 |
| VER-METHODS-014 | Verify IFC-DEFS-014: Channel calibration test injecting precision decade resistance values at the RTD element terminals and measuring signal at conditioning module output. Pass: output tracks injected resistance within ±0.5°C equivalent over full range. Verify wire balance by introducing 0.1 ohm imbalance and confirming error contribution <0.05°C. Rationale: RTD channel calibration using precision decade resistances verifies lead-wire compensation and linearisation across the full temperature range. | Test | verification, pis, rtd, session-202 |
| VER-METHODS-015 | Verify IFC-DEFS-015: Loop resistance test inserting calibrated resistance in series with each transmitter loop. Pass: 4-20mA signal stable within ±0.1% at 600 ohm total loop resistance. Verify isolation by measuring leakage current between loop and shield at 500VDC; pass: <1 microamp. Rationale: Loop resistance test validates that cable run resistance does not exceed the 600 ohm maximum, which would cause transmitter saturation and loss of signal. | Test | verification, pis, pressure, session-202 |
| VER-METHODS-016 | Verify IFC-DEFS-016: Step response test applying a 10% step change to DP transmitter input and recording time from step to 63% of final conditioned output value. Pass: 63% response time <=400ms. Verify square-root extraction linearity at 25%, 50%, 75%, 100% of span; pass: ±0.5% of reading. Rationale: Step response test measures the flow channel dynamic response to confirm the 1.0-second detection requirement for loss-of-flow protection is met. | Test | verification, pis, flow, session-202 |
| VER-METHODS-017 | Verify IFC-DEFS-017: Simulated post-accident test injecting thermocouple millivolt signals corresponding to 25°C, 100°C, and 171°C reference leg temperatures while providing known DP input. Pass: compensated level output accurate within ±5% of span at each temperature point. Verify thermocouple open-circuit detection; pass: alarm within 2 seconds. Rationale: Reference leg temperature compensation is critical for post-LOCA level accuracy; test simulates the 25-171°C range the reference leg experiences during containment heatup. | Test | verification, pis, level, session-202 |
| VER-METHODS-018 | Verify IFC-DEFS-018: Penetration assembly type test per IEEE 317 at 413 kPa and 171°C for 720 hours. Pass: insulation resistance >1 megohm between conductors and between conductor and ground. Signal integrity test measuring end-to-end attenuation at DC and 10Hz; pass: ±0.1% of span deviation from pre-penetration baseline. Rationale: Penetration assembly integrity is the containment pressure boundary; IEEE 317 type test at LOCA conditions verifies the penetration maintains its safety function. | Test | verification, pis, containment, session-202 |
| VER-METHODS-019 | Verify SUB-REQS-026: Environmental qualification type test per IEEE 323 exposing identical equipment to sequential aging, radiation (1E8 rad gamma), seismic (0.3g SSE), and LOCA simulation (171°C, 413 kPa, chemical spray). Pass: all monitored parameters remain within accuracy specifications throughout 720-hour LOCA profile. Document per IEEE 323 qualification report format. Rationale: Environmental qualification per IEEE 323 is the regulatory basis for demonstrating equipment operability under DBA conditions; sequential aging and irradiation simulate end-of-life exposure. | Test | verification, pis, containment, session-202 |
| VER-METHODS-020 | Verify IFC-DEFS-019: End-to-end channel test injecting precision millivolt signals at the thermocouple connector (simulating 200°C, 650°C, 1200°C) through the actual cable path and penetration. Pass: displayed temperature within ±4°C of injected value at each point. Verify cold junction compensation by varying panel ambient from 15°C to 40°C; pass: <1°C additional error. Rationale: MI cable-to-display path verification at simulated temperatures confirms core exit TC measurement integrity from vessel head through containment penetration to control room. | Test | verification, pams, cetc, session-202 |
| VER-METHODS-021 | Verify IFC-DEFS-020: Redundancy validation test injecting identical 4-20mA signals to both RVLIS channels and confirming displayed values agree within 2%. Inject 15% disagreement between channels and confirm flag appears on display within 5 seconds. Verify Class 1E power independence by removing power to one channel and confirming the other continues unaffected. Rationale: RVLIS redundancy validation confirms both independent channels track together, ensuring single-channel failure does not result in loss of vessel level indication. | Test | verification, pams, rvlis, session-202 |
| VER-METHODS-022 | Verify IFC-DEFS-021: Calibration gas test flowing certified 2%, 4%, 7% hydrogen-in-nitrogen through the monitor sample cell. Pass: displayed concentration within ±0.5% absolute at each point. Verify 4% alarm: inject 3.9% gas (no alarm), then 4.1% gas (alarm within 10 seconds). Verify sample system status contacts by simulating low-flow and high-moisture conditions. Rationale: Certified calibration gas at known concentrations provides traceable verification of hydrogen monitor accuracy across the 0-10% measurement range including the 4% flammability alarm point. | Test | verification, pams, hydrogen, session-202 |
| VER-METHODS-023 | Verify IFC-DEFS-022: Test battery-to-inverter interface by measuring DC bus voltage at inverter input terminals during simulated battery discharge from 140VDC to 105VDC while inverter supplies rated load. Pass: inverter output maintains 120VAC ±2% throughout discharge range. Rationale: Battery discharge simulation from 140V to 105V validates inverter operation across the full battery voltage range including end-of-discharge conditions during station blackout. | Test | verification, class1e, session-203 |
| VER-METHODS-024 | Verify IFC-DEFS-023: Test charger output by measuring float voltage at battery terminals over 24-hour period and equalise voltage during equalise charge. Measure ripple with oscilloscope at charger output. Pass: float 140VDC ±1%, equalise 150VDC ±1%, ripple ≤0.7V RMS. Rationale: Float and equalise voltage verification over 24 hours confirms charger regulation stability and ripple performance that directly affect battery life and capacity. | Test | verification, class1e, session-203 |
| VER-METHODS-025 | Verify IFC-DEFS-024: Test transfer switch response by disconnecting inverter output while monitoring downstream voltage with high-speed recorder (1ms resolution). Pass: transfer completes within 4ms, no voltage interruption exceeding 4ms at distribution panel input. Rationale: High-speed voltage recording during transfer captures the 4ms transfer time requirement; any gap exceeding protection processor ride-through causes logic reset. | Test | verification, class1e, session-203 |
| VER-METHODS-026 | Verify IFC-DEFS-025: Inspect transfer switch to distribution panel cabling for proper Class 1E identification, separation from other divisions per IEEE 384, and current rating. Verify source status indication changes when transfer occurs. Pass: all criteria met per IEEE 384 and wiring diagrams. Rationale: Physical inspection verifies IEEE 384 separation criteria which cannot be tested electrically; Class 1E identification ensures maintainers do not inadvertently cross-connect divisions. | Inspection | verification, class1e, session-203 |
| VER-METHODS-027 | Verify IFC-DEFS-026: Test branch circuit loading by measuring each load circuit current during normal plant operation. Verify selective coordination by analysis of time-current curves for branch breakers vs main breaker. Pass: all branch loads ≤80% breaker rating, coordination demonstrated for all fault levels. Rationale: Selective coordination verification under actual load conditions confirms that a branch fault trips only the local breaker, maintaining power to unaffected protection loads. | Test | verification, class1e, session-203 |
| VER-METHODS-028 | Verify SUB-REQS-035: Test battery duty cycle by performing modified performance test per IEEE 450 simulating design basis accident load profile for 4 hours. Measure terminal voltage at each load step. Pass: voltage remains ≥105VDC throughout 4-hour duty cycle. Rationale: Modified performance test per IEEE 450 with DBA load profile validates the sizing calculation and confirms 4-hour capacity with actual battery conditions including aging effects. | Test | verification, class1e, battery, session-203 |
| VER-METHODS-029 | Verify SUB-REQS-040: Inspection of divisional power supply independence by reviewing electrical single-line diagrams, physical separation analysis, and cable routing documentation. Verify no electrical interconnections between divisions or between Class 1E and non-safety power. Pass: complete independence demonstrated per IEEE 384. Rationale: Divisional independence inspection verifies IEEE 603 Clause 5.6 compliance; electrical separation cannot be fully tested without physical verification of routing and barriers. | Inspection | verification, class1e, independence, session-203 |
| VER-METHODS-030 | Verify IFC-DEFS-027: Test signal isolation by injecting a fault condition (short circuit, open circuit, ground fault) at the test module output while monitoring the process measurement channel downstream. Pass: no perturbation exceeding 0.5% of span on the process channel. Rationale: Test signal isolation must be verified under fault conditions because normal operation may not stress the isolation barrier; a fault on the test module must not propagate into the protection channel. | Test | verification, test-surv, session-203 |
| VER-METHODS-031 | Verify IFC-DEFS-028: Test optical isolation by measuring leakage current from test cabinet to protection logic under normal and fault conditions. Verify that test input injection does not alter coincidence logic output state when test inputs are inactive. Pass: leakage ≤1μA, no spurious logic state change. Rationale: Optical isolation leakage measurement under fault conditions verifies that the test cabinet cannot corrupt voting logic even during test equipment failure. | Test | verification, test-surv, session-203 |
| VER-METHODS-032 | Verify IFC-DEFS-029: Test breaker test circuit interlock by attempting simultaneous test initiation of both series breakers in a trip path. Verify the hardwired interlock prevents the second breaker test from initiating. Then verify normal single-breaker test produces breaker opening within 150ms. Pass: interlock blocks simultaneous test, single test opens breaker within 150ms. Rationale: Interlock testing prevents a procedural error from simultaneously testing both series trip breakers, which would cause a spurious reactor trip and potential fuel damage from thermal shock. | Demonstration | verification, test-surv, session-203 |
| VER-METHODS-033 | Verify IFC-DEFS-030: Test data link directionality by monitoring the communication interface during test data transmission. Verify no data can be transmitted from Communication and Display Subsystem back to the Logic Test Cabinet. Pass: hardware-enforced one-way communication confirmed by protocol analysis. Rationale: Data link directionality verification confirms no reverse path exists for test data or fault propagation from non-safety communication back to protection logic. | Test | verification, test-surv, session-203 |
| VER-METHODS-034 | Verify SUB-REQS-046: Perform overlap test analysis per IEEE 338 by documenting the test boundaries for each test type (analog channel, logic, actuator) and verifying that every link in every protection signal path from sensor to actuator is covered by at least one test. Pass: no untested gap identified in signal path coverage matrix. Rationale: IEEE 338 overlap analysis documents that no untested gaps exist between analog channel, logic, and actuator test segments; coverage gaps leave failure modes undetectable. | Analysis | verification, test-surv, session-203 |
| VER-METHODS-035 | Verify IFC-DEFS-031: Test intra-division bus timing by measuring message latency from transmitter to receiver under maximum bus loading. Inject messages at all allocated time slots simultaneously and measure worst-case delivery time. Pass: all messages delivered within ≤10ms, no message loss over 1-hour test duration. Rationale: Intra-division bus latency under maximum loading validates deterministic message delivery within the 10ms budget allocated from the system response time. | Test | verification, comm-display, session-203 |
| VER-METHODS-036 | Verify IFC-DEFS-032: Test gateway unidirectionality by attempting to transmit data from non-safety plant computer toward the safety-side gateway interface. Physical inspection of safety-side fiber optic transceiver confirms no receive photodiode installed. Pass: no data reception possible on safety side, confirmed by physical inspection and signal injection test. Rationale: Gateway unidirectionality is the primary cyber security barrier per 10 CFR 73.54; verification that no receive hardware exists on the safety side is a critical inspection. | Inspection | verification, comm-display, session-203 |
| VER-METHODS-037 | Verify IFC-DEFS-033: Test annunciator inputs by actuating each relay contact input individually and verifying correct window tile illumination, audible alarm, and first-out sequence indication. Test fault isolation by shorting an input circuit and verifying no effect on other annunciator inputs. Pass: all windows respond correctly, no cross-coupling between inputs. Rationale: Annunciator relay contact input testing verifies the diverse hardwired indication path functions independently of digital communication systems. | Test | verification, comm-display, session-203 |
| VER-METHODS-038 | Verify IFC-DEFS-034: Test SPDS data validation by providing identical test signals to two protection divisions and one deliberately offset signal to a third division. Verify SPDS correctly identifies and flags the deviant value. Pass: cross-division comparison detects deviant channel within 2 seconds. Rationale: SPDS data validation testing with deliberate offset verifies the display can identify discrepant division data, alerting operators to instrument failure during post-accident monitoring. | Test | verification, comm-display, session-203 |
| VER-METHODS-039 | Verify SUB-REQS-001: Inject step change at bistable processor input simulating setpoint exceedance and measure time to channel trip output using high-speed data acquisition (1ms resolution). Pass: trip output generated within 100ms of input reaching setpoint at 25%, 50%, and 100% of setpoint ramp rates. Repeat for all monitored parameters on each of four channels. Rationale: Bistable processor response time is the first active element in the trip chain; 100ms allocation must be verified under worst-case input conditions. | Test | verification, rts, session-204 |
| VER-METHODS-040 | Verify SUB-REQS-002: Inject two simultaneous channel trip inputs to coincidence logic module and measure time from second input assertion to train-level trip output using oscilloscope with 0.1ms resolution. Pass: trip output within 50ms. Test all 2-of-4 input combinations (6 combinations per trip function) across all trip functions. Rationale: Coincidence logic evaluation time directly determines whether the 2.0s system trip response time is achievable; 50ms allocation is verified at the train level. | Test | verification, rts, session-204 |
| VER-METHODS-041 | Verify SUB-REQS-004: De-energise reactor trip breaker undervoltage coil and measure time from coil de-energisation to breaker contact separation using auxiliary contact signal and oscilloscope. Pass: contact separation within 100ms. Verify CRDM power interruption by monitoring CRDM bus voltage. Test each breaker individually with the other breaker closed. Rationale: Trip breaker mechanical opening time is the final response time element; 100ms allocation verified by high-speed measurement from coil de-energisation to contact separation. | Test | verification, rts, session-204 |
| VER-METHODS-042 | Verify SUB-REQS-008: Inject simulated setpoint exceedance on two of four ESF channels simultaneously and measure time from second channel input to actuation demand output at ESF coincidence logic processor. Pass: actuation demand generated within 100ms. Test each ESF function (SI, CIA, CIB, CS, SLI, MFWI, AFW) independently with all 6 two-of-four input combinations. Rationale: ESF coincidence logic response time determines whether safety injection and other ESF functions meet the FSAR-assumed actuation time after setpoint exceedance. | Test | verification, esfas, session-204 |
| VER-METHODS-043 | Verify SUB-REQS-011: Simulate concurrent SI signal and LOOP condition and record load shed and reconnect sequence timing using event recorder with 10ms resolution. Pass: non-essential loads shed within 3 seconds, EDG start command issued, safety loads reconnected in sequence with minimum 5-second intervals between load steps, full sequence complete within 60 seconds. Verify no two loads connected closer than 5 seconds apart. Rationale: Load sequencing timing during simulated SI+LOOP confirms diesel generator loading stays within rated capacity and each safety load receives power within its FSAR-assumed start time. | Test | verification, esfas, session-204 |
| VER-METHODS-044 | Verify SYS-REQS-014: Cybersecurity assessment per NEI 08-09 Rev 6. Conduct vulnerability scanning of all digital safety system assets using approved security tools. Verify no external network connectivity exists by physical port inspection and network traffic capture over 72-hour period. Pass: zero external network paths detected, all unused ports physically disabled or removed, tamper indication functional on all 4 division cabinets. Rationale: Cybersecurity assessment per NEI 08-09 validates that digital safety systems meet 10 CFR 73.54 requirements; penetration testing on isolated systems verifies attack resistance. | Analysis | verification, cybersecurity, session-205 |
| VER-METHODS-045 | Verify SYS-REQS-015: D3 analysis per BTP 7-19 Appendix D. Review FPGA design tools and microprocessor compiler toolchains for tool chain diversity. Inject simulated common-cause failure scenario (all digital processors in one division producing identical incorrect output) and verify diverse manual actuation path still completes reactor trip within 2.0 seconds. Pass: documented D3 coping analysis shows diverse means exist for all Chapter 15 events, manual trip test completes with breaker opening in less than 200ms from switch actuation. Rationale: D3 analysis per BTP 7-19 verifies that no single common-cause failure of digital systems can prevent both reactor trip and ESF actuation; diverse backup paths must be demonstrated. | Analysis | verification, d3, diversity, session-205 |
| VER-METHODS-046 | Verify SYS-REQS-016: EMC qualification testing per MIL-STD-461G with test levels derived from in-plant electromagnetic survey plus 6dB margin per Regulatory Guide 1.180. Conduct radiated susceptibility (RS103), conducted susceptibility (CS101/CS114), and surge (CS116) tests on each digital safety system cabinet. Pass: no trip function degradation, no spurious actuation signals, and no communication errors during or after exposure to specified EMI levels. Rationale: EMC qualification per MIL-STD-461G with 6dB margin above in-plant survey levels ensures digital safety systems tolerate the actual electromagnetic environment including walkie-talkie and welding EMI. | Test | verification, emc, session-205 |
| VER-METHODS-047 | Verify SUB-REQS-053: Human factors validation per NUREG-0711 integrated system validation. Conduct human factors engineering verification of display character size, colour coding, and alarm prioritisation against NUREG-0700 criteria. Perform operator-in-the-loop simulation using plant-specific emergency operating procedures for LOCA, MSLB, and station blackout scenarios. Pass: all safety actions completed within analysed time margins, operator error rate below 1E-2 per critical action, no reliance on colour alone confirmed by monochrome display review. Rationale: NUREG-0711 human factors validation confirms safety display interfaces support correct operator action during high-stress post-accident conditions with acceptable error probability. | Inspection | verification, human-factors, session-205 |
| VER-METHODS-048 | Verify SUB-REQS-054: Conduct breaker interrupting capacity type test per IEEE C37.09 at rated voltage (480VAC) with calibrated load bank set to 600A. Perform 3 consecutive interruptions measuring arc duration and contact condition. Pass criteria: all 3 interruptions successful with arc duration less than 50ms and no contact welding or pitting exceeding manufacturer limits. | Test | verification, rts, breaker, session-224 |
| VER-METHODS-049 | Verify SUB-REQS-055: Conduct accelerated life test per IEEE C37.09 cycling the breaker 2000 times at rated interrupting current and 5000 times at no-load, measuring opening time at intervals of 500 cycles. Pass criteria: opening time remains below 100ms at every measurement interval, contact resistance does not increase beyond 10% of initial value, and mechanical linkage shows no measurable wear exceeding manufacturer specifications. | Test | verification, rts, breaker, session-224 |
| Requirement | Verified By | Description |
|---|---|---|
| SYS-REQS-016 | VER-METHODS-046 | |
| SYS-REQS-015 | VER-METHODS-045 | |
| SYS-REQS-014 | VER-METHODS-044 | |
| IFC-DEFS-034 | VER-METHODS-038 | |
| IFC-DEFS-033 | VER-METHODS-037 | |
| IFC-DEFS-032 | VER-METHODS-036 | |
| IFC-DEFS-031 | VER-METHODS-035 | |
| IFC-DEFS-030 | VER-METHODS-033 | |
| IFC-DEFS-029 | VER-METHODS-032 | |
| IFC-DEFS-028 | VER-METHODS-031 | |
| IFC-DEFS-027 | VER-METHODS-030 | |
| IFC-DEFS-026 | VER-METHODS-027 | |
| IFC-DEFS-025 | VER-METHODS-026 | |
| IFC-DEFS-024 | VER-METHODS-025 | |
| IFC-DEFS-023 | VER-METHODS-024 | |
| IFC-DEFS-022 | VER-METHODS-023 | |
| IFC-DEFS-021 | VER-METHODS-022 | |
| IFC-DEFS-020 | VER-METHODS-021 | |
| IFC-DEFS-019 | VER-METHODS-020 | |
| IFC-DEFS-018 | VER-METHODS-018 | |
| IFC-DEFS-017 | VER-METHODS-017 | |
| IFC-DEFS-016 | VER-METHODS-016 | |
| IFC-DEFS-015 | VER-METHODS-015 | |
| IFC-DEFS-014 | VER-METHODS-014 | |
| IFC-DEFS-013 | VER-METHODS-013 | |
| IFC-DEFS-012 | VER-METHODS-012 | |
| IFC-DEFS-011 | VER-METHODS-011 | |
| IFC-DEFS-010 | VER-METHODS-010 | |
| IFC-DEFS-009 | VER-METHODS-009 | |
| IFC-DEFS-008 | VER-METHODS-008 | |
| IFC-DEFS-007 | VER-METHODS-007 | |
| IFC-DEFS-006 | VER-METHODS-006 | |
| IFC-DEFS-005 | VER-METHODS-005 | |
| IFC-DEFS-004 | VER-METHODS-004 | |
| IFC-DEFS-003 | VER-METHODS-003 | |
| IFC-DEFS-002 | VER-METHODS-002 | |
| IFC-DEFS-001 | VER-METHODS-001 | |
| SUB-REQS-055 | VER-METHODS-049 | |
| SUB-REQS-054 | VER-METHODS-048 | |
| SUB-REQS-053 | VER-METHODS-047 | |
| SUB-REQS-011 | VER-METHODS-043 | |
| SUB-REQS-008 | VER-METHODS-042 | |
| SUB-REQS-004 | VER-METHODS-041 | |
| SUB-REQS-002 | VER-METHODS-040 | |
| SUB-REQS-001 | VER-METHODS-039 | |
| SUB-REQS-046 | VER-METHODS-034 | |
| SUB-REQS-040 | VER-METHODS-029 | |
| SUB-REQS-035 | VER-METHODS-028 | |
| SUB-REQS-026 | VER-METHODS-019 |