System

Remote Weapon Station (RWS), session 620. The {{entity:Safety Interlock System}} was completed in session 618; this session decomposes the {{entity:Fire Control System}} (SIL 2), which was pending with only a stub power requirement (SUB-REQ-011) inherited from the QC pass. Two of eight subsystems are now complete.

Decomposition

The {{entity:Fire Control System}} resolves into four components. The {{entity:Fire Control Computer}} ({{hex:51B73219}}) is the master real-time controller running the engagement sequence, sensor fusion, and pointing error loop. The {{entity:Target Tracking Processor}} ({{hex:D1F77219}}) is a separate hardware board carrying a video processing pipeline that runs the auto-tracker at 50Hz — separated from the FCC because the EOSA’s compressed video stream (IFC-REQ-007) requires processing bandwidth that exceeds the FCC’s general-purpose cores. The {{entity:Ballistic Computation Module}} ({{hex:41F73B19}}) is a software module on the FCC rather than a separate processor: the 20ms update latency from SYS-REQ-002 is achievable without inter-processor overhead, and splitting it would add failure modes for marginal benefit. The {{entity:Weapon Control Interface}} ({{hex:50F57A19}}) translates FIRE/CEASE/SAFE commands to weapon solenoid drive signals via RS-422 with galvanic isolation, protecting FCC logic from 100V switching transients.

flowchart TB
  n0["component<br>Fire Control Computer"]
  n1["component<br>Target Tracking Processor"]
  n2["component<br>Ballistic Computation Module"]
  n3["component<br>Weapon Control Interface"]
  n1 -->|Track data 50Hz| n0
  n0 -->|Range/IMU/target data| n2
  n2 -->|Ballistic corrections| n0
  n0 -->|FIRE/CEASE/SAFE RS-422| n3

Analysis

Lint flagged four high-severity findings. Two are directly in FCS scope: the {{entity:Fire Control Computer}} is classified {{trait:Powered}} with no power requirements (addressed by SUB-REQ-021: 28VDC, 8A steady-state, 15A peak) and {{trait:Functionally Autonomous}} with no safety override constraint (addressed by SUB-REQ-020: hardware watchdog at 100ms timeout forcing WCI to SAFE state). The remaining two findings — DSC and HFIR power budgets — belong to the SIS and are noted for the next QC pass. Trait similarity analysis showed {{entity:Target Tracking Processor}} at 84% Jaccard against {{entity:Dual-Channel Safety Controller}}: both are real-time, safety-relevant, digitally processing control nodes. The TTP’s image-based tracking shares the same latency-critical, fault-tolerant architecture pattern as the SIS cross-channel monitoring — a cross-domain analog suggesting the TTP should carry explicit fault-detection and output-inhibit behaviour in degraded operation, which is captured in SUB-REQ-018.

Requirements

Nine SUB requirements written: 50Hz FCC pointing loop ({{sub:SUB-REQ-013}}), TTP track accuracy ≤0.2 mrad RMS ({{sub:SUB-REQ-014}}), BCM 20ms latency ({{sub:SUB-REQ-015}}), WCI 5ms actuation latency ({{sub:SUB-REQ-016}}), FCS safe-state response to SIS assertion ({{sub:SUB-REQ-017}}), degraded mode at p≥0.5 on day channel ({{sub:SUB-REQ-018}}), 45-second BIT completion ({{sub:SUB-REQ-019}}), FCC hardware watchdog ({{sub:SUB-REQ-020}}), FCC power budget ({{sub:SUB-REQ-021}}). Three IFC requirements: TTP→FCC PCIe track data at 50Hz ({{ifc:IFC-REQ-015}}), FCC↔BCM intra-processor ballistic data interface ({{ifc:IFC-REQ-016}}), FCC→WCI RS-422 firing command link ({{ifc:IFC-REQ-017}}). Four VER entries targeting SUB-REQ-013, 015, 017, and IFC-REQ-015. Trace links connect all SUB requirements to the parent SYS requirements (SYS-REQ-001, 002, 006, 008, 011, 012) and VER to SUB/IFC.

Next

Six subsystems remain pending: {{entity:Weapon and Ammunition Handling Assembly}} (SIL 2) is highest risk and should be decomposed next. DSC and HFIR power requirements (lint findings 1 and 3) need a QC pass on the SIS. The diagCount metric (4 of 6 target) and ifcCount (17 of 20 target) will close when WAHA and Electro-Optical Sensor Assembly are decomposed.